Reverse case statement with multiple matches

[stanford]

case(1′b1) // takes 1′b1 and compares with underlying variables
var_1: <some operation> // checks if var_1==1′b1
var_2: <some operation> // checks if var_2==1′b1
default: <default operation> //if none of variable is 1′b1 then execute default
endcase

1. In such an example, what happens when both var_1 and var_2 are evaluated to be 1? Will var_1 take higher priority?

2. And why/when would you use this over if/else if/else?

 

[ads-ee]

case(1′b1) // takes 1′b1 and compares with underlying variables
var_1: <some operation> // checks if var_1==1′b1
var_2: <some operation> // checks if var_2==1′b1
default: <default operation> //if none of variable is 1′b1 then execute default
endcase

1. In such an example, what happens when both var_1 and var_2 are evaluated to be 1? Will var_1 take higher priority?

2. And why/when would you use this over if/else if/else?

This is used typically for synthesizing a one-hot fsm. By definition only one of the items is hot/active at a time. If you are worried about multiple hot bits then you need to add logic to detect that or enable synthesis to make the fsm safe.

 

[FvM]

According to LRM

The case_item_expressions shall be evaluated and then compared in the exact order in which they appear.

This answers the priority question, presumed the synthesis tool complies to the language specification.

 

[stanford]

This is used typically for synthesizing a one-hot fsm. By definition only one of the items is hot/active at a time. If you are worried about multiple hot bits then you need to add logic to detect that or enable synthesis to make the fsm safe.

What is the advantage of using reverse case statement for one hot fsm over the regular case statement?

 

[ThisIsNotSam]

What is the advantage of using reverse case statement for one hot fsm over the regular case statement?

you can show off your amazing coding skills to your colleagues, and even that is not granted because this is not easily readable.