Resize function in vhdl

[symlet]

Hai all,

I have confusion with resize function in vhdl. I have write a line of code as below:

 if even_not_odd = '0' then
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
          (RESIZE(SIGNED(romedatao(0)),DA_W) + 
          (RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0'), 
          DA_W));

When I check the result in testbench (Modelsim), the value of dcto_1 is 384. However, I aspect the value will be 256 (128+128). I attach the figure,hope anyone can figure it out for me. Thanks in advance.

 

[FvM]

The question is almost meaningless without telling the data type of the involved signals.

But generally speaking, resize cuts or extends a numerical signal (signed or unsigned) on the left and doesn't change it's value as long as it fits the new data size. Concatenating a zero at the right side is effectively a multiply times 2, if 2*128=256 still fits the resized number, the sum will be 384, as observed.

 

[symlet]

The question is almost meaningless without telling the data type of the involved signals.

But generally speaking, resize cuts or extends a numerical signal (signed or unsigned) on the left and doesn't change it's value as long as it fits the new data size. Concatenating a zero at the right side is effectively a multiply times 2, if 2*128=256 still fits the resized number, the sum will be 384, as observed.

Hai FvM,

Below is the data types of the signals:
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal romedatao : array(0 to 7) of STD_LOGIC_VECTOR(13 downto 0);
constant DA_W : INTEGER := 22;

I understand now why the sum is 384. As you said concetrating a zero at the right is a multiply times 2. If I have a line code as below, is it the operation of multiply times 2 is same as before? Eventhough the number of zero is increase (not same as before)? Thanks in advance.

dcto_2 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_1) +
          (RESIZE(SIGNED(romedatao_d1(2)),DA_W-2) & "00") +
          (RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000"),
          DA_W));

 

[TrickyDicky]

appending each '0' is like a multiply by 2. So romedatao_d1(2) is multiplied by 4 and romedatao_d1(3) by 8.

Out of interest, why are you casting it all back to std_logic_vector? why not just store the values as signed?

 

[symlet]

appending each '0' is like a multiply by 2. So romedatao_d1(2) is multiplied by 4 and romedatao_d1(3) by 8.

Out of interest, why are you casting it all back to std_logic_vector? why not just store the values as signed?

Hai TrickyDicky,

Actually, I use std_logic_vector at all my operation (others port map). That why I casting it back to the same data type. Btw, thanks for reply, I understand about the adding zero in the line code now. Thanks in advance.

 

[TrickyDicky]

You dont need to have everything in std_logic_vector - you are allowed to use signed on ports. it saves a lot of type conversions.

 

[symlet]

You dont need to have everything in std_logic_vector - you are allowed to use signed on ports. it saves a lot of type conversions.

Hai TrickyDicky,

Thanks for your suggestion. I would try it. Thanks