So while I was working for layout in Tsmc 5/4 I encountered something that I didn't before, at any other node. Here the resistor started from M5/M6 so you could place logic devices under them(but you cannot route on M5/M6 on the resistor area and cannot have M5M6 powergrid there as well ).
Any idea on how they made it physically on these layers? Is it just resisistive layers on the same height as M5/M6 ?
This sounds like special high-resistivity (and possibly high precision) resistors, formed by special layer, placed between M5 and M6, similar to MIM capacitor layers.
They are useful for various applications, such as for current sensing in power FETs.
That's why one cannot draw M5 and M6 lines over that area, but can use that area for FEOl devices deep underneath.
Since you have an access to this PDK, just open the Electrical Design Rule Manual, and search for these resistors - he description should explain this well.
You can also open up Calibre SVRF rule file, and see how these devices are formed, recognized, layer connectivity, etc.