Re: reset synchronizer -Digital Synchronizer without Metastability
Thought you might find this interesting if you have not seen it before:
Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
https://www.techbriefs.com/component/content/article/5617Authors: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009
Publication Year: 2009
Document ID: 20090032096
Subject Category: TECHNOLOGY UTILIZATION AND SURFACE TRANSPORTATION
Report/Patent Number: MSC-23220-1
Publication Information: NASA Tech Briefs, September 2009; 12; Number of pages = 1
Language: English
Subject Terms: CLOCKS; DIGITAL ELECTRONICS; DISCRIMINATORS; FAILURE; LOGIC CIRCUITS; METASTABLE STATE; PULSE DURATION; SYNCHRONIZERS
Accessibility: Unclassified; Publicly available; Unlimited; Copyright, Distribution as joint owner in the copyright
Document Source: CASI
Updated/Added to NTRS: Sep 11, 2009
Who knows how to implement reset synchronizer to avoid metastability of asynchronized reset? And why asynchronized reset is metastable?
- - - Updated - - -
Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
http://www.techbriefs.com/component/content/article/5617Author: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009
- - - Updated - - -
Thought you might find this interesting if you have not seen it before:
Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
http://www.techbriefs.com/component/...e/5617Authors: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009
Publication Year: 2009
Document ID: 20090032096
Subject Category: TECHNOLOGY UTILIZATION AND SURFACE TRANSPORTATION
Report/Patent Number: MSC-23220-1
Publication Information: NASA Tech Briefs, September 2009; 12; Number of pages = 1
Language: English
Subject Terms: CLOCKS; DIGITAL ELECTRONICS; DISCRIMINATORS; FAILURE; LOGIC CIRCUITS; METASTABLE STATE; PULSE DURATION; SYNCHRONIZERS
Accessibility: Unclassified; Publicly available; Unlimited; Copyright, Distribution as joint owner in the copyright
Document Source: CASI
Updated/Added to NTRS: Sep 11, 2009
Originally Posted by zhaoyimiao
Who knows how to implement reset synchronizer to avoid metastability of asynchronized reset? And why asynchronized reset is metastable?
- - - Updated - - -
Title: Digital Synchronizer without Metastability
Online Source: Click to View PDF File [PDF Size: 103 KB]
http://www.techbriefs.com/component/content/article/5617Author: Simle, Robert M.; Cavazos, Jose A.
Abstract: A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Collection: NASA
NASA Center: Johnson Space Center
Publication Date: September 2009