Request help on Charge Pump Circuit

[civic78]

Good Day,

Presently, I am designing a Charge Pump for usage in PLL.
But had encountered some challenges.
The Vout constantly increases regardless of the Up or Down pulse width variation.
My understanding was that with Up pulse wider than Down pulse, Vout would increase.
Down pulse wider than Up pulse, Vout would decrease and when both is equal width, the Vout will be stable.

Would appreciate your advices. Thanks.

 

[kenambo]

sorry i think i didnt understand ur question...

But i am just telling you about the Up and down pulses,,,,,

Actually, CPD generates either up pulse or DOWN pulse according to the Phase and frequency of the reference clock and feedback clock...

BUT, we introduce a small delay which is called reset delay in both UP and Down pulses, So the capacitor is either charging or discharging while the UP and Down pulses....

In this circuit also same thing will happen... Maybe you can choose correct Capacitor for charging and discharging..

hope this helps you, any doubts let me know..

thanks

 

[Guillermo80]

Hi, I think you will probably have to change the connection of C1 in your Loop filter.
I would connect it instead to Vout and GND.
Also you should check the values you assigned to the capacitors and the resistor in your design to match your time requirements.