req: vhdl spi interface for resolver (e.g. ad2s 12-series)

[nicklas_a74]

I need a simple spi interface to be implemented in a cpld to enable
communication with a tracking resolver (e.g. ad2s 12-series, read serial data as speed, angular position and writing resolver settings).

Does anyone have a vhdl file that gives a good starting point? Also a model for a resolver in vhdl that could be used in a TB (test) would be helpful.

Thank you

 

[FvM]

Requirements for ADC SPI interface are quite different, e.g. high or low clock speed, addressable registers to serve, one or several output channels.

My suggestion is to write it from the scratch based on your specific needs.

- clock generation. for slow and medium speed, the clock is send from a register in your SPI interface, for high speed the system clock copied to SCLK

- frame generation, e.g. a state machine with a bit counter

- a shift register for SDI and SDO