i am looking for VCD standard document! However i sense that it has not been standardized by IEEE. Probably any official doc (e.g. from Verilog engineers that pioneered VCD) would do.
PS: Is there any good parser tool for reading/writing VCD. I am also looking for formal docs (as above).
This code must be added to each Verilog testbench in order for a VCD file to be generated.
// The following code will generate a VCD file containing
// all of the nets in the instance t.uut. "t" is the module name of the
// testfixture, "uut" is the instance name
// of the design being tested.
initial begin
$dumpfile("invchn26.vcd"); // Change filename as appropriate.
$dumpvars(1, t.uut);
end