[Req] Testbench by using system verilog with ModelSim

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elektrom

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Can you give me an example?
 

I think ModelSim don't support systemverilog fully.
 

I saw from its datasheet that systemverilog 3.0 is supported, not 3.1 which is use for making test bench. Is it correct?
 

elektrom said:
I saw from its datasheet that systemverilog 3.0 is supported, not 3.1 which is use for making test bench. Is it correct?

Yes most of systemverilog 3.1 are used for verification
 

you need to wait modelsim 6.1, I think
 

hi,

i think modelsim 6.0 will support
systemverilog.please try to verify the dataheet

with regards,
kul.
 

Yes modelsim 6.0 supports SystemVerilog!
you can check running following examples...
**broken link removed**
 

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