removing spurs from passive PLL filter

[banner]

spur problem

Hi,
i have a problem with spur in a passive loop filter PLL. input oscillator is 102.4MHz, while PFD input is 25.6 MHz. output of the PLL is 1800MHz. the loop is locked and thare are 2 spurs in addiition to the main carrier. they are in frequencies 1800+/- 102.4. when you change the input frequency to 25.6MHz and PFD frequency to 25.6MHz. they came to the distance of +/-25.6MHz of the carrier. i don know how to remove the spurs. is it possible that it is a PFD or PCB problem?

 

[vfone]

Re: spur problem

Always the reference spurs appears at the output of the PLL…more or less…depending by the characteristic of the LPF loop filter.
Generally the cut-off frequency of the LPF should be 1/10 of the reference frequency.
PCB layout (and grounding) could influence the spurs at the output of the PLL, especially when the reference is high, as in your case.
Also check the power supply decoupling of both, PLL and reference. The grounding of the decoupling caps of these supplies needs careful design.

 

[biff44]

Re: spur problem

I would suspect a grounding problem. You reference clock is leaking onto the VCO somehow. Being that it is 100 MHz, it should be fairly easy to fix, though. Make sure the pll is well grounded, make sure there are plenty of chip caps (0.1 uF, 4.7 uF) peppered around the circuit. Maybe you should isolate the power supply from the VCO by using a small (5 ohm) series resistor and then shunt caps very close to the VCO. Finally, you can make a simple R-C lowpass filter, with a cuttoff frequency of around 3 MHz, that should keep any possible 100 MHz glitches off the VCO tune line (one again, the C mounted as close as possible to the VCO).