# registered inout in verilog

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#### buenos

##### Advanced Member level 3
hi

i have a bidirectional 32bit bus.
this has to be driven directly from a statemachine, and not from an assign statement. The reason is to decrease the clock-to-output static timing.
In VHDL, this works fine, but in verilog it gives me errors.
If i define the bus as reg, it complains that reg can not be bidirectional, if i dont the it complains about something else.

so, how take drive the bidir bus directly from the statemachine, and how to define the port for that?

#### mrflibble

##### Advanced Member level 5
so, how take drive the bidir bus directly from the statemachine, and how to define the port for that?
Using an assign?

The only way I know in fpga country for an inout, you will have to put the pin into high-Z when operating as an input. And drive it with the output value when operating as an output.

Which means an assign like:

Code:
wire my_output_pad;

my_io_pad = (output_enabled) ? (output_value) : (1'bz);
and for the input:

Code:
wire my_input;

my_input = my_io_pad;

---------- Post added at 16:52 ---------- Previous post was at 16:49 ----------

Also see my post here: https://www.edaboard.com/thread159731-2.html#post889894

same thing...

#### muni123

##### Member level 3
You cannot directly drive that inout from teh statemachine, definitely need to declare it as wire in verilog.

#### FvM

##### Super Moderator
Staff member
The reason is to decrease the clock-to-output static timing.
You shouldn't expect, that the synthesis tool cares for your behavioral coding style when optimizing timing. Simply use the syntax required by the Verilog standard. Timing is a different thing.

#### buenos

##### Advanced Member level 3
in vhdl i can drive inouts directly, even to "ZZZZ".

For example : drive output "data_bus" if a=b and d=15.
If we drive it directly from the statemachine, then the combinatorial part will be conencted before a flipflop, while if we add the combinatorial assigment into an assign, then it will be after the output of the flipflop adding the delay into that and not the previous FF-to-FF timing path. It is desirable not to add any decoding into the path that goes off-chip.

anyway, i have generated a decoded oe signal in the statemachine then used the assign to to drive the output when oe=1.
so its solved.
unfortunatelly none of the replies suggested this solution, but its not a problem anymore.

#### FvM

##### Super Moderator
Staff member
while if we add the combinatorial assigment into an assign, then it will be after the output of the flipflop adding the delay into that and not the previous FF-to-FF timing path. It is desirable not to add any decoding into the path that goes off-chip.
The suggested construct

my_io_pad = (output_enabled) ? (output_value) : (1'bz);

does not add any delay after the FF. It simply infers a threestate output and hasn't to do with "decoding". That's why I mentioned, the synthesis tool doesn't care for your behavioral coding style. Of course, I can't predict the exact results of your synthesis tool, but it's very likely to happen with currently available tools. Or did you find a different result in gatelevel net lists of your tool?

Depending on the target hardware, there may be specific options like implementing the FF in an output register rather than a logic cell. If it's not choosen automatically due to your timing constraints, specific synthesis attributes may be required to achieve it.

#### mrflibble

##### Advanced Member level 5
anyway, i have generated a decoded oe signal in the statemachine then used the assign to to drive the output when oe=1.
Amusingly enough, that is precisely what this infers:

Code:
my_io_pad = (output_enabled) ? (output_value) : (1'bz);
After synthesis, just check out the technology schematic... As FvM pointed out, it will infer a tristate output. No additional combinatorial logic adding delays in any way...

Anyways, you got it working, so like you say problem solved!

#### buenos

##### Advanced Member level 3
sorry, i was thinking on something like this:
my_io_pad = (a==b && c==1'b1 && d[3:0]==4'b1010) ? (output_value) : (1'bz);

so then i replaced it by this:
-------------------------------
my_io_pad = (output_enabled) ? (output_value) : (1'bz);
...
//statemachine...
..state 1
if (a==b && c==1'b1 && d[3:0]==4'b1010) begin output_enabled <= 1'b0 end
...
...state2
if (e==1'b0) begin output_enabled <= 1'b1 end
...
//state machine end

...

#### FvM

##### Super Moderator
Staff member
Driving a output_enabled in the state machine will be faster, if it's implemented as a register, in other words, assigned in an edge sensitive always block.

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