Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register with Enable Race Condition

Not open for further replies.


Newbie level 1
Feb 5, 2013
Reaction score
Trophy points
Activity points
This may be a dumb question, here is the scenario:

I have a register with enable (call it RegA).

The input put of RegA is pulled high permanently.

Meanwhile, the enable line of RegA is connected to the output of RegB through some simple combinational logic.

Now in the scenario, on the next clock pulse the output of RegB will will go high for just one clock cycle.

My question is, will I see the output of RegA go high in the same clock cycle that RegB goes high, OR will RegA go high on the next clock cycle, OR is it possible that it may never go high due to a race condition?

From experience, I feel like RegA will go high on the same clock cycle that RegB goes high, however, I'm wondering if this is bad practice and unreliable. I'm thinking there could be a race condition between the signal getting to enable line and the clock edge to RegA going high. Since the enable line goes through some combinational logic, it would seem it would loose that race every time and thus RegA wouldn't recognize that the enable line is high in the same clock cycle that RegB goes high.

I'm a newbie, so sorry if this is a silly question.

Thanks, Mark

Use blocking statements for coding Reg A Block you will not see the issue.

Not open for further replies.

Part and Inventory Search

Welcome to