register inputs on rising edge and outputs on falling edge

[shaiko]

Hello,

What are the benefits of registering the outputs of our FPGA on the falling edge of the clock?

 

[milind.a.kulkarni]

As per I know....Falling Edge registering will be implemented when you want to have half clock cycle dealy between the input to be registered....

 

[shaiko]

So the only reason to do it is to save on a single latency level?

 

[TrickyDicky]

you cannot use both clock edges in an FPGA. you will need a 2x clock to do this.

 

[Alosevskoy]

Registers in IOBs can be configured as DDR Register which toggles at the rise and the fall edge of the same clock.

 

[shaiko]

TrickyDicky,

What do you mean?
Suppose, we have 2 separate output ports.
You're saying we can't use rising_edge(clk) to register the first and falling_edge(clk) for the other?

 

[dll_fpga]

No.Thats not possible with a single clock.Either register on the rising or falling edge......

TrickyDicky,

What do you mean?
Suppose, we have 2 separate output ports.
You're saying we can't use rising_edge(clk) to register the first and falling_edge(clk) for the other?

 

[shaiko]

I'm a little confused.
I'm seen designs that use both rising and falling edge FFs. All of them had only one clock source...they compile and synthesize with no special problem.

 

[mrflibble]

Assuming we're talking fpga's here. As far as I know a single fabric flipflop can only clock on one single edge. Of course you can make a design with 1 single clock and 2 flipflops. Flipflop A clocks on the posedge, and FF B clocks on the negedge. This can be done. You cannot however make FF A (or B for that matter) clock on BOTH the posedge and the negedge. Remember, this is for fabric FFs.

Now for IO you have DDR registers, and those CAN clock on both the posedge and the negedge. But those FFs are located around the edges of the fpga only, and are meant for IO. So for the bulk of your flipflops you are limited to one single clock edge for any given flipflop.

Hope that clarifies things...

---------- Post added at 11:36 ---------- Previous post was at 11:32 ----------

Oh yeah, and to clarify on the "1 single clock and designs that clock on both the posedge and the negedge" situation. This can be done, using one single clock net. For example on spartan-6 you have local clock inversion per slice. So while using just 1 global clock net you can still have the FFs in slice A clock on the posedge, and the FFs in some other slice B clock on the negedge. For older fpga's like the spartan-3 no such local clock inversion, so in that case you would need 2 clock nets.

 

[shaiko]

Again,
I'm not talking about a DDR flip flop!

To elaborae:

Suppose, A is an input pin to the FPGA and B is an output port.

-- first process
if rising_edge(clk) then
internal_sig_1 <= A;
end if;


-- second process
if falling_edge(clk) then
B <= internal_sig_2;
end if;

This is what I meant. I see no reason why it can't be done.

 

[FvM]

Yes, you can of course clock different FFs on different edges. You have been however asking "What are the benefits". There's no general benefit, I think. It serves a purpose in special cases. Do you imagine a special application that makes you think of using different clock edges?

 

[mrflibble]

Again, I understand from your ambiguous post that you indeed may or may not have been interested in DDR FFs. Which is precisely why I handled both cases. Even starting out with regular flipflops... So just reread, and ignore the second half about DDR that you turn out not to be interested in.

Here, let me make it even easier. It's this bit:

Assuming we're talking fpga's here. As far as I know a single fabric flipflop can only clock on one single edge. Of course you can make a design with 1 single clock and 2 flipflops. Flipflop A clocks on the posedge, and FF B clocks on the negedge. This can be done. You cannot however make FF A (or B for that matter) clock on BOTH the posedge and the negedge. Remember, this is for fabric FFs.

There we go. And fabric FFs == the regular boring FFs that are not DDR flipflops.

And the VHDL code you posted is indeed precisely what I described in the above quote. So short version: yes, that can be done.

 

[dll_fpga]

This can be done ,as they are different flipflops but whats the advantage u see?

Again,
I'm not talking about a DDR flip flop!

To elaborae:

Suppose, A is an input pin to the FPGA and B is an output port.

-- first process
if rising_edge(clk) then
internal_sig_1 <= A;
end if;


-- second process
if falling_edge(clk) then
B <= internal_sig_2;
end if;

This is what I meant. I see no reason why it can't be done.

 

[mrflibble]

There's no general benefit, I think. It serves a purpose in special cases. Do you imagine a special application that makes you think of using different clock edges?

This can be done ,as they are different flipflops but whats the advantage u see?

I can't think of any general benefits either. I can think of a specific case...

I had this ethernet PHY chip once, where the fpga inputs (PHY status bits and such) were sampled on the posedge. Internal logic on the posedge as well. And the fpga outputs fifo output data transition was done on the negedge.

---------- Post added at 14:20 ---------- Previous post was at 14:11 ----------

Forgot to mention: Amusingly enough, I used DDR registers for the output since that made clock alignment easier. Oh the irony!

 

[milind.a.kulkarni]

Apart from the dealy I think negative edge sampling is used for registering the differential signal also.....

Good Luck

 

[shaiko]

Thanks for the answers!