xtal feedback resistor
Hi,
I have a few more queries.
The crystal manufacturer specifies the vales of C1,C2 (Load) and the crystal parameters (R,L,C and C0). This would give a particular phae shift (pi network). Now there would be some more additional capacitances like input capacitances, PCB trace capacitances and bond pad capacitances that would be added along with the crystal load, which means that the pahse changes to some other values since the valus of CL gets altered due to these parasitic elements. Now which needs to be adjusted to compensate for the phase errors. I mean where do you have the control to alter the pahse chages in the circuit. Is that phase chages would be adjusted automatically with the feedback loop and nothing need to be done?.
Kindly explain me on this.
thanks®ads,
sridharan
Added after 2 hours 27 minutes:
Hi,
I have one more doubt.
What would be the problem in designing crystal IO for 1.8V,2.5V and 3.3V (Multiple voltage domain). Can I have parallel stack and achive the same Gm?.
can anyone please answer this?.