Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Regarding vhdl component - port map

Status
Not open for further replies.

nesta

Junior Member level 2
Joined
Feb 19, 2010
Messages
20
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,466
Hi vhdlExperts,

I am not a very experienced vhdl programmer and i have some doubts on the component instantiation & port mapping.

I have an entity declared in file1 as:
----------------------------------------------
entity gate_2 is
port(bit_in : IN std_logic_vector(2 downto 0);
bit_out : OUT std_logic
);

end entity;
---------------------------------------------

and i need to use this entity to design another circuit which has a 8-bit input. I need to connect only 3 of this input bits to the gate_2 entity shown above..

the current way i am doing is as shown below:
-------------------------------------------------

architecture behavioral of gateCkt is
-- assign bit 4,2,1 to the gate
component gate_2
port( a : IN std_logic_vector(2 downto 0);
x : OUT std_logic);

signal c_sig : IN std_logic_vector(2 downto 0);

begin
c_sig(0) <= b(4);
c_sig(1) <= b(2);
c_sig(2) <= b(1);

U1: gate_2 port map(a => c_sig, x => xout);


-------------------------------------------------

My question is , is there a way to directly map the bit inputs to the gate_2 a input port..

like gate2 port map( a => b(4,2,1)....
something like this..

I am not finding an elegant way to do this..

Please suggest.

Thanks,
Nesta
 

CoryUT

Newbie level 3
Joined
Jul 31, 2006
Messages
3
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,296
Hi Nesta,

The only alternative I can think of would be to use the '&' operator to concatenate the bits within your port map:

U1: gate_2 port map(a => b(1) & b(2) & b(4), x => xout);

Alternatively -

U1: gate_2 port map(b(1) & b(2) & b(4), xout);

Also remember to take note of your vector directions. Say b(4,2,1) were syntactically correct. The mapping a => b(4,2,1) would map:
a(2) => b(4)
a(1) => b(2)
a(0) => b(1)
The opposite of your explicit list.

Hope this helps! I'm no expert myself, so maybe someone will come along with a more elegant solution.

-Cory
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,049
Helped
2,072
Reputation
4,161
Reaction score
2,024
Trophy points
1,393
Activity points
38,913
is this elegant enough?

Code:
gate2 port map (
  a(2) => b(1),
  a(1) => b(2),
  a(2) => b(4)
);
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top