module fix(x,z,x1
);inputsigned[4:0]x;output z;outputsigned[14:0]x1;localparamsigned[11:0] y =12'b100000000000;reg[14:0]z;always@*begin
z=x*y;end// selecting msb reg z1;always@*begin
z1=x[4];end// to check if number is positive or negative reg[14:0]x1;always@( z or z1)beginif(z1 ==1)
x1 =~z;else
x1 = z;endendmodule
this is the code to get one input .. can anyone help me in iterating this code so as to get 32 inputs... many thanks in advance....
You don't iterate code (sounds like a sw coder writing verilog) you either use a generate-for loop or have an fsm that time shares a resource.
Here is the format for a generate-for loop to create 32 instances of some block of code.
Code Verilog - [expand]
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generategenvar i;for(i=0;i<32;i=i+1)begin: gen_inputs
// your code goes hereend
I'm not even sure what the point of this code is. A simple shift is all your really need here and an inversion (one's complement?) based on bit four of the input vector.
This code doesn't look like it takes into account what hardware is generated from synthesis.
This makes me question Verilog's aliasing rules. For example, z -- a 1 bit wire -- has the same name as z -- a 15 bit signed reg. Does verilog allow this and what does this mean?