Regarding the samples bypass vhdl code

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Maitry07

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Hello support team,

I am getting output samples ( 1 sample width : 16 bits) with a rate of 61.44 MSPS in below repetative form.

Sample 0 = correct output​
sample 1 = no output​
sample 2 = no output​
sample 3= correct output. and so on.....​

So, here my requirement is to bypass sample 1 and 2 and move forward the sample 0 and 3. so my output would become sample0,3, 6, 9, 12,15,..... like this.

Could you please suggest a suitable logic in order to apply above.
Awaited your response.
 

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yes, I am also thinking of counter. I have tried but not getting the proper result. may be there is some issue of falling edge and rising edge. could you please suggest?
I am getting counter divider 0 and 2 only.
--- Updated ---

I have attached the screenshot of my output samples without implementation of counter.
sig_m_axis_dout_tdata_1[15:0] = as you can see after every 2 samples, I am getting one correct sample.

Let me give you breif, My div_out_0 and div_out_1 are the I and Q samples , which I am providing to the CORDIC to get SQRT(I^2+Q^2).
I_hex = 2280
Q_hex=oeba
CORDIC output in hex = 2582

So, I want to add one counter at the CORDIC output, in which I can bypass the 2 samples out of total 4 samples.

 
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The basic idea is that you need a modulo-3 up counter (i.e. 0 - 2). Initialize it to 2 for the initial sample S0. All samples at count 2 are valid.

6.144/3 = 2.048 MSPS, which is still a whole number.

It could actually be a multiple of mod-3. But the basic idea is that you need a mod-3 counter.
 
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Hello

Thank you for your response. I will try this.
--- Updated ---

We can say this as one kind of filtering, right?
 
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Hi
I'm not sure about the initialization value in this formula. Can you explain more?
 

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initial zero will do. It is implementation issue to choose valid sample anyway.
Very simple.

index ------logic-------- count(2 bits)
s0 ---------- pass ------- 0
s1---------- mute--------1
s2 ---------- mute ------- 2 and then force to 0 instead of 3
 

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