Regarding the digital gain compensation in FPGA

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Maitry07

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Hello support team,

I have a fixed gain RF chain at the input of RF-ADC(high speed data converter) , and RF-ADC has inbuilt DDC , which convert RF input direct to I, Q samples. From the I,Q samples I am using CORDIC IP core for the conversion of I, Q to amplitude and phase.
But as the original RF input amplitude is modified due to fixed gain RF chain, I want to compensate for that fixed RF gain , so that I can get the exact amplitude after CORDIC.
So, for that in between DDC output(I, Q samples) and CORDIC input , I need to add digital gain compensation algorithm.
Could anyone suggest a suitable way to do this digital gain compensation?
My RF input is sine wave ( no modulation)- 65 MHz frequency.
 

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