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Regarding tapeout using cadence- help neede urgent.

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parthi2311

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Hello everyone,

I hope someone ll probably help me.

I am currently doing masters in VLSI systems. My final year project work is done and the design is ready. My design's post layout simulation results are absolutely fine.I want to tapeout the design.But i have very little idea regrading the tapeout. I did the layout using cadence virtuso and the technology i am working on is umc 0.18um cmos. Is there any material that ll guide me to tape out my design . Right now i have the rc extracted files. How to go ahead from here? Please help. I ll be grateful to you.
 

putturvenkatesh

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Tape out is procedure to send for fabrication. This is very costly for an individual to go for. Check if your College has some tie-up with umc fab. Then talk to your prof and get some silicon area booked in the next test chip.
 

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