I wanted to know what all is there to know about synthesis of HDLs pls. I recently went to an interview and I was told that I don’t know anything about synthesis (I basically knew what synthesis in HDLs mean and could only translate simple behavioral models in logic gate circuits).
Hence pls. tell me what all to know about synthesis from present day work point of view. Any starting pointers would be appreciated.
I wanted to know what all is there to know about synthesis of HDLs pls. I recently went to an interview and I was told that I don’t know anything about synthesis (I basically knew what synthesis in HDLs mean and could only translate simple behavioral models in logic gate circuits).
Hence pls. tell me what all to know about synthesis from present day work point of view. Any starting pointers would be appreciated.
learn what the inputs are: RTL description, library, constraints
learn what the outputs are: mapped netlist
learn the tricks in the middle: clock gating, retiming, scan insertion, power analysis, timing analysis
in the process, try to pick up on the terminology. you don't synthesize HDLs. the same way you don't compile C++s. you synthesize a piece of code that happens to be written in an HDL.
There is part of VHDL/Verilog that is simulation only. There is a part that could synthesize, but doesn't synthesize by all tools. There is a final part that can synthesize, but possibly should not. There are also ways to write some code where the code synthesizes but is unlikely to work.
OK. What should I read (and more importantly from where) to know more about synthesis in VHDL? Also are there any tools which are specifically used for synthesis of VHDL codes? Any free tools in that direction?
OK. What should I read (and more importantly from where) to know more about synthesis in VHDL? Also are there any tools which are specifically used for synthesis of VHDL codes? Any free tools in that direction?
Understanding synthesis and understanding the language are two different things. To understand synthesis you want to understand digital logic, how digital logic works and what's possible.
Think of it like architecture: You can draw a skyscraper that's 100 miles tall but if you give it to a contractor he won't be able to build it. That's the relationship between the HDL language and the synthesis tool.