There are many other methods than sizing to fix setup violations.
1. Logic restructuring: Reduce combinational logic delay by minimising number of logic levels.
2. Vt swapping: Sweeping HVT by RVT or LVT. Standard cell library has three type of cells. HVT(High threshold voltage), RVT (Regular threshold voltage), LVT (Low threshold voltage). These have drive strength in increasing order starting from HVT > RVT > LVT.
3. Buffering: Put buffer if there is a long net in layout or a net have high fanout.
4. Pin swapping: Delay from input to output is different for different input to output arcs due to on time resistance of transistors in the cell.
5. You use skew to meet setup time. This concept is called useful skew.
If you have doubt related to any point, let me know I'll try explain that in a elaborate way.