Hi,
The data input to my core will be through LVDS interface (BT656 format with EAV,SAV etc.) I am told. That is all the info I have. Some clock recovery has to be done I guess and further the data has to be deserialized and passed onto my core.
I tried to refer to some of the clock recovery techniques however I could not find a proper completely digital CDR ckt. I am not sure if PLL based can be implemented on an FPGA.
Kindly do let me know if there is a completely "Digital" solution to clock recovery without the use of PLL even if it is jitter prone.