Regarding PSL Assertion

[verma.ind]

Hi.....

I have to check(assertion) interface signals between two modules.
Where i can write the assertion so that i can check the interface?
I cannot write it any of these module because i will not be able to access the other module signals?
Can anybody helps me...

Thanks

 

[aji_vlsi]

Hi.....

I have to check(assertion) interface signals between two modules.
Where i can write the assertion so that i can check the interface?
I cannot write it any of these module because i will not be able to access the other module signals?
Can anybody helps me...

Thanks

If it is really "interface" signal, it should be visible in both modules. Anyway, why not just write it at top level where both modules are instantiated?

Ajeetha, CVC
www.noveldv.com

 

[tarunmakwana]

Hi.....

I have to check(assertion) interface signals between two modules.
Where i can write the assertion so that i can check the interface?
I cannot write it any of these module because i will not be able to access the other module signals?
Can anybody helps me...

Thanks

u can directly access the interface signals by
interface_instacename.propertyname

 

[verma.ind]

At the top level also same problem is coming, i can only access the top module signal, not the instantiated module signal, giving undefined signal error.

i will give u one example:

"RXActive" is a top level signal and is interfacing signal.

.rxactive(RXActive): here i m instantiating the above signal in one of module.

When i m writing the assertion for this signal, it's giving the error as rxactive not defined.
How to write the assertion for this signal?

 

[skygazer]

RXActive is a signal in the top level module and rxactive is defined in the instantiated module. Thats why rxactive is not visible in the top module and you are getting a error.
You may assert RXAactive and monitor it becoz anyway rxactive is tied to RXActive..

 

[verma.ind]

Can anybody tell me is it useful to write assertion for checking the crc?

 

[verma.ind]

I am writing psl assertion for interfacing signals from one module to another module.
Like if Module A has signal sigA1 which is connected to Module B of signal sigB1, then i have written

property prop1 = always (A.sigA1 == B.sigB1)@(posedge CLK);
assert prop1;

Whether this is the correct way to write for interface signal or any other method we can use?
Also Whether this type of assertions are useful or not?

Thanks

 

[aji_vlsi]

I am writing psl assertion for interfacing signals from one module to another module.
Like if Module A has signal sigA1 which is connected to Module B of signal sigB1, then i have written

property prop1 = always (A.sigA1 == B.sigB1)@(posedge CLK);
assert prop1;

Whether this is the correct way to write for interface signal or any other method we can use?
Also Whether this type of assertions are useful or not?

Thanks

Consider using standard checker libraries for this sort of simple and often used checks. For instance you can use assert_always checker from OVL for this one. OVL is an Accellera standard and is supported by all tools. Do a google search to find more if needed.

Also Whether this type of assertions are useful or not?

That's not so easy to answer. If you are new to ABV, then it is a good idea. And having so many of these light weight assertions really help. tehre are stats saying ARM uses 2000+ assert_always, Intel uses some huge number etc. Such checks are useful for IP intergators usually.

Ajeetha, CVC
www.noveldv.com

 

[verma.ind]

Hi.....

What is fairness and starvation in verification and how i can check this fairness problems with assertions?

Thanks