In 10 years of FPGA design, I have never run a post synth simulation.
All bugs are either RTL bugs or poor timing specs.
As long as you follow good practice (everything synchronous etc) you shouldnt need a post synth sim.
Until the day you hit a synthesisor bug.... (though apparently nowhere near as common as it used to be - but we have a design that currently works with chipscope and fails without, so synth problems me be occuring. We're not doing post synth sims though).
Unlike Tricky I've been doing this for 2x longer and used to always run a post synth and a post map simulation because synthesis tools and vendor mapping tools sometimes would mess up and change the design so it would no longer work. For the past 10 years I have only run post synth or netlist simulations (after mapping/routing) on only a small number of occasions when the design wasn't behaving in circuit as simulation predicted. In most of those cases it was either a difference in the interface protocol or something that was misinterpreted in a spec. In only a few instances was it something to do with the actual synthesis and/or the mapping of logic.
The majority of the problem with running gate level simulations is time. Most of my HDL designs are so large they may take upwards of 2-3 hours to run a testcase. The same testcaes run as a gate level simulation will take 2-3 time longer. So basically I have to run it overnight...and inevitably (given Murphy's law) it breaks 10 minutes after I leave work. Have that happen multiple days in a row and you start to question the usefulness of always doing a gate level simulation.
Nothing wrong with abusing fpga's for async. As long as you do it on purpose, and with a purpose. The misery and loss is when you accidentally make things asynchronous in your design where you really intended synchronous. Here latchy latchy...