regarding OCV and uncertainity

[venkatramanan]

IN ocv analysis why we are using setup check for max value and hold check for min value.?

after cts the uncertaintiy value tool ll take from the sdc file?what is the effect of uncertainity value after cts?

in ocv analysis we are using single lib or multiple lib?
ple any one explain me....

 

[childs]

In OCV (On Chip Variation), we assume things can be very different within the chip, under single operating condition. So to simulate the most pessimistic case for:
- setup: assume data launch path is really slow & data capture path is really fast.
- hold: assume data launch path is really fast & data capture path is really slow.
There are few different ways as far as I know to do this:
- use multiple libraries (eg: slow & fast lib at single operating condition)
- use single library & apply derate

Meanwhile I am not really sure about the uncertainty after cts. I am guessing the uncertainty will add up uncertainties from all clock buffers & nets inserted. Again I am not sure, pls do not take this as final

 

[ivlsi]

apply derate

How do you do that? What is "derate"?

use multiple libraries (eg: slow & fast lib at single operating condition)

Hm... After P&R, is provided for STA. As far as I know, RC-extraction includes all the timing arcs in the design (including the cells also)... So, how do you use the tech libs (*.lib) in the Post-P&R STA? Are they ever needed?

Thank you!

 

[rca]

the OCV is also the idea to have timing variation in the same chip of the same std cell dependant where this one are placed.
Due to local voltage drop not equivalent, technology variation...