regarding number of LUTs and SLICES

[me0414013]

SIR i tried to implement triple modular reduntant mux4:1... but after repeating the hardware 3 times and passing it through voter also its showing the same number of slices and luts... why is it happening so...? is it all because of rooting algorithm????or is it minimizing the logic...? (since i have to compare area*time for the two muxes)

 

[HMS1021]

It is likely it is being optimized (minimized) away. You may need to change the optimizer settings although it is typically better to use the right variable types and architecture to prevent this from happening. Most IDEs have an option to produce a report during each step including synthesis. The report will tell you specifically what was deleted if anything.

 

[me0414013]

It is likely it is being optimized (minimized) away. You may need to change the optimizer settings although it is typically better to use the right variable types and architecture to prevent this from happening. Most IDEs have an option to produce a report during each step including synthesis. The report will tell you specifically what was deleted if anything.

sir can u brief about "right variable types and architecture" ?.... thanks in advance..

 

[HMS1021]

The details depend on whether you are using VHDL or Verilog, the IDE in use, what the target device is, etc.
You need to find and understand the IDE set up options and how the various data types are handled.
Did you locate and review the synthesis report as suggested?