srini.pes
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Hi all.,
Am designing 8-point DHT using EDK..
In my design having 8-i/p's[4 bits each] and 8-o/p's [8 bits each]...
While in my user_logic.vhd file.,only one input and output were there to write data and read data from/to FIFO..IP2RFIFO_Data......,
How to write different number of inputs to a FIFO at a time and how to read from the FIFO...
Is it possible to increase the number of FIFO in the design..
How to write those data into the memory and to read from the memory...
Is it possible to control the address of the FIFO in this code. ??
Thanking u all..........
Please give me some suggestions...
Am designing 8-point DHT using EDK..
In my design having 8-i/p's[4 bits each] and 8-o/p's [8 bits each]...
While in my user_logic.vhd file.,only one input and output were there to write data and read data from/to FIFO..IP2RFIFO_Data......,
How to write different number of inputs to a FIFO at a time and how to read from the FIFO...
Is it possible to increase the number of FIFO in the design..
How to write those data into the memory and to read from the memory...
Is it possible to control the address of the FIFO in this code. ??
Thanking u all..........
Please give me some suggestions...
