Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Regarding circuit design

Yash0425

Newbie
Joined
Jun 22, 2022
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
21
Hi , I am new to this kind of forum and I am going to industry newly so I want to learn about designing. There are many threads and article about gm/Id method of designing so my doubt is what is the general method or way of approaching the design problems(fro specs like ft, supply voltage, power, f3dB) to aspect ratios of transistors do we definitely follow any methodology?

Any reference will also be helpful ....plz mention the source (as in guideline it is mentioned that posting books/PDFs will result in ban from forum) TIA
 

pankajpc

Junior Member level 1
Joined
Aug 22, 2014
Messages
18
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,283
Activity points
1,427
Hi , I am new to this kind of forum and I am going to industry newly so I want to learn about designing. There are many threads and article about gm/Id method of designing so my doubt is what is the general method or way of approaching the design problems(fro specs like ft, supply voltage, power, f3dB) to aspect ratios of transistors do we definitely follow any methodology?

Any reference will also be helpful ....plz mention the source (as in guideline it is mentioned that posting books/PDFs will result in ban from forum) TIA
gm/Id by boser please refer to the same.
--- Updated ---

you can use gm/id by boser or you can use the standard design techniques. but sometimes gm/id is recommended.
 
Last edited:

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,806
Helped
2,221
Reputation
4,448
Reaction score
2,159
Trophy points
1,393
Location
USA
Activity points
62,452
To me the whole "gm/Id" thing is about giving professors
something to teach, but falls apart as soon as you encounter
real transistor nonidealities. Probably half a dozen op amp
designs taken to production (as piece parts or embedded to
larger products) and never once bothered with the textbook
(or rather textbooks which appeared well after I graduated)
approach.


"It is like a finger pointing away to the moon...
... do not concentrate on the finger or you will miss all the
heavenly glory"

- Bruce Lee, "Enter the Dragon"
 

24BSNR

Junior Member level 1
Joined
Apr 9, 2022
Messages
15
Helped
1
Reputation
2
Reaction score
3
Trophy points
3
Activity points
36
I think a lot of analog designers will struggle with gm/Id because programming isn't exactly their forte. You have to be able to develop tables to work with based on your process and tools that you are comfortable with, and then be able to set up the problems in a way that matches the tools and how well you understand the circuit and test benches already. If you can't design an opamp without using gm/Id already, you will likely struggle when using the method. Managers love the idea, because it gives them the illusion that design cycles can be much faster and easier.

On the other hand it can be very useful since 1) it uses the same process files that designers simulate around anyways. 2) can reduce the number of design variables to start iterating over (e.g. starting with a simple gm/Id target already eliminates one of the two variables once you know the other).

On the other hand, in my experience of designing for production over many years, I can't say that your managers will start by giving you all the nice specs and constraints up front (power, area, f3db, fu, etc.), that would be nice. But it's more like, we need a 6 or 7 bit ADC for the ethernet front end receiver, how long will it take you to design it? The big struggle is figuring out how to even translate that to specs (which includes learning how to ask others for help, and hopefully getting it).
 
Last edited:

pankajpc

Junior Member level 1
Joined
Aug 22, 2014
Messages
18
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,283
Activity points
1,427
by standard design techniques, I mean putting all the transistors in saturation and designing the opamp.
 

fire_bolt

Junior Member level 2
Joined
Jul 24, 2015
Messages
21
Helped
2
Reputation
4
Reaction score
3
Trophy points
3
Activity points
145
For higher tech nodes => 130nm , Id equations will help. Calculations will match your simulation results. But for lower tech nodes, lambda effect is more. Simulations are based on higher order equations. So, first analyse the simulation results of single nmos/pmos circuits. Apply these learning on bigger circuits. Keep current mirrors with large L & low gm to improve rout. Keep input & cascode devices with higher gm for better gain. Always start with min W/L sizes. Hope this helps.
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top