regarding architecture of vhdl

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u24c02

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Hi

In the vhdl, i have question about variable_for in the following code.

Code:
..
..
Entity rtl is


End entity
Architecture ttt of rtl is
bigin
variable_for :
...
...

end architecture;

What is variable_for? What is function?



And i have one more question

How can i vhdl shm dump in vhdl code?
 
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