Hi
I am using altera Ip core for the first time . I had generated ddr2 controller IP from altera and I have to run it by using MODELSIM whether to check it is working r not . But I am unable to do it. Can any help in this regard,,,,,,
I am newbie to this tool and i am running Modelsim in LINUX . There I added library files altera_mf.v 220model.v sgate.v . so apart form this what to do can u please guide me..
Hi,
first change the project directory of modelsim to project_folder -> testbench->modelsim.
then in command window type the following.
set memory_mode_xxx.v
where xxx.v is the behavioral model of the memory you are using.
source yyy.tcl
where yyy.tcl is the core generated tcl script which u'll find in the testbench->modelsim folder.
If any issues pls ask ur querries...
i am currently working on it... and i took hell lot of time to start with simulation... everything was missing for me then
Regards
Hi,
did u try what i have said...???
first open the modelsim...
then change the directory to the path where the modelsim folder is generated by the core.[u can change the directory by open modelsim->Files->Change Directory->browse the folder said]
Then type "set memory_model ddr2.v"(dont use inverted commas) in modelsin command window, where ddr2.v is the behavioral model of the your memory device which u can download from the corresponding memory device vendor. Next u shud make suitable changes in the core generated testbench according to the model which u have downloaded, i.e., in the testbench u have to instantiate the downloaded memory model.
Then run the core generated tcl script for simulation by command:
source *.tcl where *.tcl is found in the core generated modelsim folder.
Properly follow the above three steps and get the project simulated
All the best
Thanks and Regards
Then run the core generated tcl script for simulation by command:
source *.tcl where *.tcl is found in the core generated modelsim folder.
Properly follow the above three steps and get the project simulated
All the best
Thanks and Regards[/quote]
Hi param ,
Thank you for responding, I had done same thing u had said.........
But I am getting following error
Error: (vsim-3033) ../../ddr2_ctrl_auk_ddr_sdram.v(250): Instantiation of 'auk_ddr_controller' failed. The design unit was not found.
I am using in verilog and this was not generated in verilog model instead it generated in vhdl
If you follow the user guild, there should be no problem.
One thing you need to make sure that you don't
use the DDR2 synthesis file when you do simulation.
you should use xx.vo (simulation) file not xx.v (synthesis) file. I remember "auk_ddr_controller" is for synthesis.