Jul 5, 2012 #1 K kumar781 Newbie level 5 Joined Jul 5, 2012 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,322 what are the recent trends in low power vlsi cmos design ?
Jul 6, 2012 #2 V vijay.mani884 Member level 5 Joined May 23, 2012 Messages 81 Helped 16 Reputation 32 Reaction score 16 Trophy points 1,288 Activity points 1,789 clock gating cells level shifters retention flops
Jul 6, 2012 #3 yadavvlsi Advanced Member level 3 Joined Nov 19, 2010 Messages 977 Helped 487 Reputation 972 Reaction score 459 Trophy points 1,343 Location Bangalore, India Activity points 6,991 Check this: https://www.scribd.com/doc/23999148/Trends-in-Low-Power-VLSI-Design
Jul 16, 2012 #4 K kumar781 Newbie level 5 Joined Jul 5, 2012 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,322 Thanks for the reply Do you know anything About power gating techniques and presently i want to do my project in low power cmos design can you suggest how to proceed
Thanks for the reply Do you know anything About power gating techniques and presently i want to do my project in low power cmos design can you suggest how to proceed
Jul 17, 2012 #5 S sakthikumaran87 Full Member level 3 Joined Nov 9, 2009 Messages 160 Helped 21 Reputation 42 Reaction score 21 Trophy points 1,298 Location India Activity points 2,176 go through synopsys low power design manual. u can find detailed description on power gating techniques.
go through synopsys low power design manual. u can find detailed description on power gating techniques.