reg vlsi low power cmos design

[kumar781]

what are the recent trends in low power vlsi cmos design ?

 

[vijay.mani884]

clock gating cells
level shifters
retention flops

 

[yadavvlsi]

Check this:
https://www.scribd.com/doc/23999148/Trends-in-Low-Power-VLSI-Design

 

[kumar781]

Thanks for the reply


Do you know anything About power gating techniques

and presently i want to do my project in low power cmos design can you suggest how to proceed

 

[sakthikumaran87]

go through synopsys low power design manual. u can find detailed description on power gating techniques.