reg t output setup fixing

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pavi622

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Hi,
i am working with SoC encounter for PD. For a particular design after PD, when verified for timing am getting to many reg to output setup violations. I cant upsize the cells as the cells used are of maximum drive stregnth. So is it some how possible so that i can controle the PD optimization flow so that set up violations is removed.

Thanks
 

Check the path if there are too many buffers in that path. If yes, also check how many nets they are being connected to. If there are unnecessary buffers that are not affecting other paths and if they are not affecting hold violations in that path, you may try to remove them.
 

How to know whether the buffers inserted are unnecessary or not and do not affect other paths?
 

check with designer is those reg2out paths are valid and need fixing.? make sure you are putting realisitc set_output_delay
 

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