Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

reg t output setup fixing

Status
Not open for further replies.
P

pavi622

Junior Member level 1
Joined
Apr 2, 2012
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,400
Hi,
i am working with SoC encounter for PD. For a particular design after PD, when verified for timing am getting to many reg to output setup violations. I cant upsize the cells as the cells used are of maximum drive stregnth. So is it some how possible so that i can controle the PD optimization flow so that set up violations is removed.

Thanks
 

Check the path if there are too many buffers in that path. If yes, also check how many nets they are being connected to. If there are unnecessary buffers that are not affecting other paths and if they are not affecting hold violations in that path, you may try to remove them.
 

How to know whether the buffers inserted are unnecessary or not and do not affect other paths?
 

check with designer is those reg2out paths are valid and need fixing.? make sure you are putting realisitc set_output_delay
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top