Reg syn temp set / reset Issue

[sureshaa]

Hi all,

I having one soft reset in my system.But some of the block needs the reset release after some time of soft reset release. For that I am using like below,

temp_rst_n <= sys_rst_n and temp_enable;

In my system(totally 60 blocks), within that 20 blocks are used the temp_rst_n as reset but all others will work at sys_rst_n.I didnt use the global reset for those 20 blocks.I have use the temp_rst_n as below,

process(clk,temp_rst_n )
begin
if(temp_rst_n ='0')then
assignments;
else rising_edge (clk) then
assignments;
end if;
end process;

Whether it will leads to problem? please share me any documents regarding the above issue.

thanks and regards,
Suresh.A

 

[mrflibble]

Whether it will leads to problem? please share me any documents regarding the above issue.

The concept of having an input reset signal, and then deriving other resets from that? There's nothing inherently wrong with that. You may want to look into "asynchronous assert, synchronous de-assert" of your resets incidentally. And the stuff in quotes googles fairly well.

 

[TrickyDicky]

It will depend on what architecture you're using. Xilinx have sync resets on their flops, whereas altera have to emulate sync resets, but do have async resets. As long as the reset is synchronised, then using an async reset should be no problem, especially in altera. in Xilinx you should really use sync resets.

 

[mrflibble]

On xilinx you can have sync or async reset, depending on configuration. But for a FF in a synchronous part of the design I always use the sync reset option. And as hinted at, the reset inputs from outside of the fpga can be asserted async, just make sure the de-assertion happens synchronously or you can get all sorts of fun stuff. There's a good paper on that somewhere....

update .. this is the one I meant: http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf

 

[ads_ee]

You should also note that Xilinx uses active high resets and sets, Altera uses active low resets and sets. If you implement the code posted (with active low reset) in a Xilinx part you'll end up with an inverter in the reset path that will be connected to the output of the reset circuit register (using the information in the link mrfibble provided).

 

[sureshaa]

Thanks folks.. Now I got clarification.. I am using Altera FPGA only. But one more doubt whether these kind of reset tree wont affect the "removal time"?

 

[mrflibble]

What do you mean by "removal time"? De-assertion of reset?

 

[sureshaa]

What do you mean by "removal time"? De-assertion of reset?

yeah.. I mean reset recovery time and removal time.