In SoC Encounter, CTS can be done in two modes :
1. Manual 2. Automatic
In manual mode, we have to specify the clock name, no. of levels, buffer to be used at each level and some other parameters.
In automatic mode, we can generate a clock specification file template and edit it if required, and use it for synthesizing the clock tree.
Use "ckSynthesis" command to synthesize the clock tree according to the specifications.
If there is a data path between two clock domains, we have to optimize the delays between both the trees by grouping both the clocks.
"ckSynthesis -check" gives the trace report in a file .cts_trace
The tool traces the clock tree automatically starting from the root pin.
CTS on gated clocks can be performed automatically. There is a parameter "NoGating" in the clock tree specification file which controls the CTS on gated clocks. If NoGating is set to no, (NoGating NO), skew balancing is not performed for the gated clock
.