reg and wire of verilog programming

[Vimalab]

reg [3:0]cval.
wire [3:0]quot.

what is the initial value of cval and quot in verilog programming?

 

[rberek]

reg does not have a default initial value. You have to give it one. In simulation, if a register is unintitalized, it will appear as 'X'.

Wires do not have the ability to hold a state. A wire will always take on the value of whatever it is connected to.

r.b.