Hello kk913913,
The topology you have attached only permits an output voltage reference equal to ~ 1.2 [V]. Therefore, it is impossible to design it using VDD >1.2 [V].(for instance, 1.6 V). Some times, 0.13 um processes have I/O devices whose VDD is nearly 1.8 or 2.5 volts, or even 3.3.Check if you have these devices, if yes, so you can use them and design your circuit.
If the process does not allow for them, you need to change the topology. You can use MOSFETs working in Subthreshold region and then , achieve an output voltage less than 1.2 [v],
Take a look on this traditional topology: A CMOS Bandgap Reference Circuit with Sub-1-V Operation
Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba,
Toru Tanzawa, Shigeru Atsumi, and Koji Sakui.
It works for your case.
I hope it helps,