Reference VHDL constants in Verilog

[Lucian Mru]

Hello !

I just started using verilog and I want to use constants defined in an VHDL package inside a verilog test-bench. I'm not even sure if that is even possible. Any hint would be appreciated.

I'm using Cadence® Incisive® Enterprise Simulator.


Thanks!
Lucian

 

[FvM]

Write a VHDL wrapper component that returns the constant values as output signals. It can be instantiated in the verilog testbench.

 

[ahmad1954]

in verilog with `include you can enter a file to your design.