You mean you are designing your own chip?
In general, the applicaton designates the reference frequency. If you want low phase noise, you try to go with a high one (100 to 500 MHz at the phase detector). If you have a commercial application, you probably have somewhere between 1 KHz to 20 Mhz at the phase detector. Remember, most PLLs divide down the reference frequency to a lower number than what the crystal oscillator is running at.
If you have a specific application in mind, make up a spread sheet of the desired VCO output frequencies, and figure out what PD operating frequency makes the most sense for the step sized needed, the programmability allowed, and the noise/spurs desired.