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# Reference frequency of PLL

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#### Engineer4ever

##### Member level 3
Hi,

I am designing a PFD and I was wondering how can I determine the value of the reference frequency? I know that the crystal oscillators generate frequencies in MHz range, but how to determine the exact value. Are there other parameters that could help define that value?

You mean you are designing your own chip?

In general, the applicaton designates the reference frequency. If you want low phase noise, you try to go with a high one (100 to 500 MHz at the phase detector). If you have a commercial application, you probably have somewhere between 1 KHz to 20 Mhz at the phase detector. Remember, most PLLs divide down the reference frequency to a lower number than what the crystal oscillator is running at.

If you have a specific application in mind, make up a spread sheet of the desired VCO output frequencies, and figure out what PD operating frequency makes the most sense for the step sized needed, the programmability allowed, and the noise/spurs desired.

In case of integer PLL, the phase detector frequency (PDF) is given by

PDF = reference frequency/R = output frequency/N

where R and N are integers.

This means that, for integer PLL, the reference frequency must be a multiple of the PDF. The same for the output frequency.
PDF defines the minimum channel spacing.

So, does that mean that I decide the value of N first then I calculate the value of the reference frequency? I thought it was the opposite.

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You mean you are designing your own chip?

In general, the applicaton designates the reference frequency. If you want low phase noise, you try to go with a high one (100 to 500 MHz at the phase detector). If you have a commercial application, you probably have somewhere between 1 KHz to 20 Mhz at the phase detector. Remember, most PLLs divide down the reference frequency to a lower number than what the crystal oscillator is running at.

If you have a specific application in mind, make up a spread sheet of the desired VCO output frequencies, and figure out what PD operating frequency makes the most sense for the step sized needed, the programmability allowed, and the noise/spurs desired.

No, it's not my own chip. It's a big project and I am designing the PFD+CP+LF.

The VCO o/p required frequency should be 5 Ghz, so do I need the step size also to determine the exact value of the reference frequency? I am sorry but I just feel I am a little lost and I don't know which parameters should be given and which parameters should I find by myself.

Have you got to generate just a single frequency or many channels equally spaced ?
If, for example you have to generate many frequency spaced by 25 kHz at 5 GHz using an integer PLL, then

PDF = 25 kHz
Reference frequency = 25 kHz*R
Output frequency = 25 kHz*N

Supposing R ranges between 1 and 2000, then 25 kHz < Reference frequency < 50 MHz
Supposing N ranges between 1 and 300000, then 25 kHz < Output frequency < 7.5 GHz --> OK counter is large enough

Just an example. For detailed informations about PLL the Dean Banerjee book is very clear and complete.

Have you got to generate just a single frequency or many channels equally spaced ?
If, for example you have to generate many frequency spaced by 25 kHz at 5 GHz using an integer PLL, then

PDF = 25 kHz
Reference frequency = 25 kHz*R
Output frequency = 25 kHz*N

Supposing R ranges between 1 and 2000, then 25 kHz < Reference frequency < 50 MHz
Supposing N ranges between 1 and 300000, then 25 kHz < Output frequency < 7.5 GHz --> OK counter is large enough

Just an example. For detailed informations about PLL the Dean Banerjee book is very clear and complete.

I need two clocks; one of GHz and the other of 2.5GHz. The VCO should generate 5GHz and be connected directly to the buffer to be distributed, and the VCO will also be connected to a divider-by-2 to generate 2.5GHz. So, I guess that means that I have to generate only one frequency which is 5GHz.

So, I guess that means that I have to generate only one frequency which is 5GHz.
Yes, I think so.

Well, if you do not have any other cares, why not choose the reference frequency to be 20 MHz, and the N=250.

If your phase lock loop will not allow an N that low, divide down the reference to maybe 2 MHz, and use an N=2500.

Got it. Thanks for your replies

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