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Reference driver for negative/above rail voltages.

saqib.shah06

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I am currently working on the design of a reference buffer for a Sigma Delta.
I came across the TI ADS1248 (datasheet here) . It seems that the chip can accept negative voltage references below ground (AVSS-100mV), as well as postive voltage references above AVDD (AVDD+100mV).
Doing this with a normal unity gain OPMAP would seem impossible (cannot drive the outputs completely to either rail). Does anyone have some sort of idea, of how such a thing can be accomplished? Seems a swtiched cap front might be able to do it, albeit at the cost of an input current.

Thanks!
 

BradtheRad

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Out-of-bounds voltages can be level-shifted by mixing with (say) 1/2 supply_V, through a resistive divider. It can lift a negative voltage up into the positive region. The IC might contain such a network internally, invisibly.
 

saqib.shah06

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Out-of-bounds voltages can be level-shifted by mixing with (say) 1/2 supply_V, through a resistive divider. It can lift a negative voltage up into the positive region. The IC might contain such a network internally, invisibly.
Doing this would draw a current from the reference, something that might not be desired since the reference voltage might change. E.g., in the datasheet, the current drawn from the reference is only 30 nA
 

FvM

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Rail-to-rail voltage range of reference inputs is no reason to use actually a reference voltage at or even beyond the rails. Other criteria (available reference source and buffer) have to be considered as well. What are you exactly trying to achieve? Application examples in datasheet are assuming a reference voltage within rails, e.g. 2.5V. What's your intended reference source?
 

BradtheRad

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The tiny 30 nA draw suggests a component at the input which is voltage controlled rather than current controlled. A component that comes to mind is depletion-mode jfet. (Example, TL081 series op amps are fet-input.)

N-fet does not turn off until bias voltage is in the negative polarity, meaning below ground rail by a volt or 2.

Similarly P-fet remains On while bias voltage is less than upper supply rail. To turn it entirely off you must apply bias voltage which is a volt or 2 greater than supply rail.
 

saqib.shah06

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Rail-to-rail voltage range of reference inputs is no reason to use actually a reference voltage at or even beyond the rails. Other criteria (available reference source and buffer) have to be considered as well. What are you exactly trying to achieve? Application examples in datasheet are assuming a reference voltage within rails, e.g. 2.5V. What's your intended reference source?
I am sorry, but I didn't quite understand your first statement.
My actual inquiry was about how to accommodate the negative reference. Assuming, e.g., I want to use a negativ reference of -100 mV and a positive reference of 1.25 (hence a net differential reference which is still within the rails). It seems that it is not possible to do it with a conventional CMOS circuit unless some sort of level shifting was designed. This obviously would come with its own set of headaches (noise, offset, etc) so it might not be desirable.
 

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I want to use a negativ reference of -100 mV and a positive reference of 1.25
To achieve what? You can surely do if it serves a purpose in your design but you need an additional negative supply.

It's not unusual to have additional supply voltages for the analog signal conditioning circuit in front of an ADC.
 

danadakk

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Common mode outside rails comes in handy for current sensing applications.

Are you seeking external G to get both dynamic range and resolution ? If
so there are processors out there that have onboard 20 bit with 100 mV
outside rail and onboard Vref.....

1655374066893.png


Regards, Dana.
 

saqib.shah06

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To achieve what? You can surely do if it serves a purpose in your design but you need an additional negative supply.

It's not unusual to have additional supply voltages for the analog signal conditioning circuit in front of an ADC.
I am not actually designing for such a voltage reference range (hence, the assumption part). I was merely curious how one can do it (if at all) using a normal CMOS process.
I assume also, that there are uses for such scenarios (I am not aware of them) and that is why they have designed with such specs.
--- Updated ---

The tiny 30 nA draw suggests a component at the input which is voltage controlled rather than current controlled. A component that comes to mind is depletion-mode jfet. (Example, TL081 series op amps are fet-input.)

N-fet does not turn off until bias voltage is in the negative polarity, meaning below ground rail by a volt or 2.

Similarly P-fet remains On while bias voltage is less than upper supply rail. To turn it entirely off you must apply bias voltage which is a volt or 2 greater than supply rail.
--- Updated ---

The tiny 30 nA draw suggests a component at the input which is voltage controlled rather than current controlled. A component that comes to mind is depletion-mode jfet. (Example, TL081 series op amps are fet-input.)

N-fet does not turn off until bias voltage is in the negative polarity, meaning below ground rail by a volt or 2.

Similarly P-fet remains On while bias voltage is less than upper supply rail. To turn it entirely off you must apply bias voltage which is a volt or 2 greater than supply rail.
Thanks for your insight, Brad.
Another possibility that I just cam across is that a charge pump could be used in the output stage of the opamp (the input should be able to handle ADD+100m/ AVSS-100m if using a complementary N/P diff pair).
 
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d123

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Hi,

100+ pages of datasheet :)... WRT Vrefs +-100mV > V+ and < gnd, are you sure you are not misunderstanding that it seems to refer to avoiding unintentional excursions beyond supply rails to avoid turning on the ESD diodes? It describes this roughly 1/3rd of way through datasheet.

Also, I have seen quite a few IC schematic depictions in datasheets, etc., that - as you just said - show the use of positive and negative charge pumps to expand what the IC can handle (maybe even for 'over-the-top' operation or to create true R2R in and/or out functionality. Like Doctor Who's TARDIS - bigger on the inside than on the outside, and deceptively so from external appearance. Device you link to shows no internal charge pumps in the block diagrams till where I stopped skim-reading, at least.
 

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Hi,

You've probably already seen all this stuff before, but just in case...

figures 1, 2, 4 and whole text is interesting

figure 1

TI RRIO OA pdf is block diagram on page 18 with internal charge pump, AD RRIO OA is simplified schematic on page 13, Silicon Labs OA is page 7 'Theory of Operation' bit.

These are all normal RR'IO'. I could swear in recent months I saw true, as in truly, RRIO device with internal pos and neg charge pumps in a datasheet for something but I must be wrong as nothing showed up now...
 

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saqib.shah06

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Hi,

You've probably already seen all this stuff before, but just in case...

figures 1, 2, 4 and whole text is interesting

figure 1

TI RRIO OA pdf is block diagram on page 18 with internal charge pump, AD RRIO OA is simplified schematic on page 13, Silicon Labs OA is page 7 'Theory of Operation' bit.

These are all normal RR'IO'. I could swear in recent months I saw true, as in truly, RRIO device with internal pos and neg charge pumps in a datasheet for something but I must be wrong as nothing showed up now...
Hi,
Thanks for your insight.
For the TI RRIO, the input stage does indeed use a charge pump to eliminate the complementary differential pair distortion problem.
This is what I was referring to my earlier post (#9), I was wondering if using a charge pump in the output stage might help the output to swing beyond the rail.
 

FvM

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For the TI RRIO, the input stage does indeed use a charge pump to eliminate the complementary differential pair distortion problem.
Which TI amplifier do you refer to? I'm not aware of types with built-in charge pump.

RR output means in usual understanding that the output swings near to supply rails, but not beyond.
 

d123

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This is what I was referring to my earlier post (#9), I was wondering if using a charge pump in the output stage might help the output to swing beyond the rail.

Hi,

Sorry for delay in answering. I really don't know. I wonder that (/a similar aspect) as well - if no RRIO is ever actually RRO because of Vce(sat) or Rds(on), why not use internal charge pumps to make say IC internal rails V+ and V- x 1.1 or 1.05 to accomodate this 'shortcoming', for example. Maybe there's some reason no-one makes them (OA is hard to compensate or has unmanagable overshoots or extended can't fit extended internal V- to circuit ground without degraded performance or something or other else), so perhaps rephrasing question is more apt - since it must have crossed many people's, particularly designers, minds besides yours and mine, why don't ICs with this feature exist?

As you will have a better idea than I ever will, do you see it slotting into an OA design comfortably without bringing a host of problems (every problem has a solution, but every solution brings its own problems, some of which are worse to wrestle with than just sourly accepting the original problem with its imperfection)?
--- Updated ---

Which TI amplifier do you refer to? I'm not aware of types with built-in charge pump.

RR output means in usual understanding that the output swings near to supply rails, but not beyond.
Hi,

OPA4388 is one, datasheet is at bottom of post #11, page 18 block diagram.
 

d123

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