Hi i am designing a PLL for 100mhz spec and i am using ring VCO in my design. i ve put some seven stages for my design and i ve used NMOS to control voltage.. I am gettin the spec frequency but the problem i face is tat ripples occur in waveform.. can anybody suggest me a method to reduc ethe ripples
to reduce the ripple on the control voltage size the capacitor to filter the ripple.In a second order loop filter the second pole should be sized to filter out the ripple.