I have a design which consists of 7 sets of push wheel switches, each set with 4 digit. The digital parallel outputs from these switches amounts to 16 X 7!
Is there a way to minimize wiring requirements. I was thinking of a serial shift register. Any ideas?
Not sure what your switches look like. Isn't each digit four outputs and one common? If so, you could tie the four outputs of each digit together (i.e., 1 to 1, 2 to 2) then you would just need 28 commons and 4 outputs. You could further reduce the wires by using a 5:32 decoder to drive the commons==>9 wires.
Calculating the minimum lines with simple multiplexing technology:
16 × 7 = 112 lines
Sqrt(112) = something with 10.x
This means 11 + 11 = 22 signal lines.
The absolute minimum is a 7 to 128 decoder --> 7 outputs + 1 input = 8 lines.
Or a 6 to 64 with 2 inputs.
In either case you need 112 diodes to combine the signals.
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For sure one can think of some more intelligent solutions:
* dedicated multiplexing IC similar to those in PC keyboards.
* or a solution with resistors and ADC...
In the end Barry's solution (but with the diodes) maybe is the most useful.
Diodes? What diodes? All you need is to drive each of 28 commons individually and wire-or the four BCD outputs of each digit. (This presumes the undriven commons float.)
But a 112-bit shift register would be the absolute minimum wire count: Latch clock, data. You could do this in a CPLD.
Two BCD switches. Each with 4 outputs
Now assume the left one shows "0x1" and the right one "0xF".
Obviously the right one shorts all the BCD lines independent if it´s COM is selected or not.
--> if COM1 is selected, all BCD outputs are acitve, instead of only line "1".
Two BCD switches. Each with 4 outputs
Now assume the left one shows "0x1" and the right one "0xF". View attachment 146697
Obviously the right one shorts all the BCD lines independent if it´s COM is selected or not.
--> if COM1 is selected, all BCD outputs are acitve, instead of only line "1".
144 pin CPLD has 80 fewer pins than fourteen 16-pin devices. And less board space. But this is all kind of academic without knowing what the OPs intent is. Is this a high-production design? A hobby thing?
The question at all does not provide enough information to evaluate the suited solution. Depending on the distance, the wirings, the Vdd power level, and the change rate of the switches status, this can limit the implementation of some solutions. In particular, whenever possible I prefer the solution based on parallel input type 74xx373, once with this approach it is possible to repeat the reading in only one clock cycle, just to confirm the correctness of the previous reading.
Hi
Thanks to everyone for giving excellent insight into this problem. Push wheel switches are passive and non volatile . In my application, I am prohibited to use memory devices. Now I have to decide between 373 vs shift register approach. 373 would add 16 outputs+ 7 enable signals. Shift register if cascaded as long shift register would take only 1 output (SO)+1 clk+1shift/ld ( common to 7 SR's)