Madhub
Newbie level 2
Hi,
I am using Reduced Media Independent Interface (RMII) in my design. For this, I am giving a 25 MHz crystal to Ethernet PHY chip. The chip has a 1.2 V internal regulator and generates the required 50 MHz clock required for RMII and this is fed to the processor. My question is, how this 50 MHz helps to generate 100Mbps speed from Processor to PHY and vice-versa ?
Regards,
Madhu
I am using Reduced Media Independent Interface (RMII) in my design. For this, I am giving a 25 MHz crystal to Ethernet PHY chip. The chip has a 1.2 V internal regulator and generates the required 50 MHz clock required for RMII and this is fed to the processor. My question is, how this 50 MHz helps to generate 100Mbps speed from Processor to PHY and vice-versa ?
Regards,
Madhu