Hi,
There r few techniqes to reduce power at various levels, i.e dynamic power, as static power is not in our hands.
And this dynamic power depends on the voltage and switching activity. So at architecture level make sure that few modules work while other modules need to be inunworking stage so that voltage do not pass through these modules and seperate the clock using modules with the other one as the switching activity of the clock is constant and even make use of gray code style in some of the modules, and also gated clocks if possible.
Bye
take care.