Feb 13, 2006 #1 O OvErFlO Full Member level 3 Joined Dec 7, 2001 Messages 178 Helped 7 Reputation 14 Reaction score 3 Trophy points 1,298 Activity points 1,342 I have this configuration, I have see a little output noise (Vpp_noise = 100mV) on the first AOP. (see image below) **broken link removed** The second amplify is a AOP inverted mode with an Vo = -10* Vi, my second amplify bounce also noise, there's a metod to reduce noise ? thanks
I have this configuration, I have see a little output noise (Vpp_noise = 100mV) on the first AOP. (see image below) **broken link removed** The second amplify is a AOP inverted mode with an Vo = -10* Vi, my second amplify bounce also noise, there's a metod to reduce noise ? thanks
Feb 14, 2006 #2 J jayc Member level 3 Joined Feb 14, 2006 Messages 64 Helped 11 Reputation 22 Reaction score 0 Trophy points 1,286 Activity points 2,007 What if you try using an ideal Op-Amp?
Feb 14, 2006 #3 eecs4ever Full Member level 3 Joined Jan 31, 2006 Messages 176 Helped 28 Reputation 56 Reaction score 10 Trophy points 1,298 Location Analog Environment Activity points 2,838 100 mV is pretty large. Maybe using ideal op-amps could isolate where the noise is coming from? Try adding some capacitance at that node to see that helps.
100 mV is pretty large. Maybe using ideal op-amps could isolate where the noise is coming from? Try adding some capacitance at that node to see that helps.
Feb 14, 2006 #4 J jcpu Full Member level 4 Joined Dec 17, 2005 Messages 214 Helped 18 Reputation 36 Reaction score 5 Trophy points 1,298 Activity points 2,968 Dear OvErFlO: Please tell the start and stop frequency. But 100mV is really large. You might want to check correctness of the noise model by simulating stand alone transistor.
Dear OvErFlO: Please tell the start and stop frequency. But 100mV is really large. You might want to check correctness of the noise model by simulating stand alone transistor.