Reduce FM PLL noise

[Synaps3]

I am using one of those all in one FM stereo transmitter chips. It works very well, but there is a lot of phase noise from the PLL. The chip's default crystal clock speed is 32khz, but the datasheet says the device can be programed for several crystals all the way up to 38.4mhz. Would increasing the clock speed reduce the PLL noise in any way? Is there any other way to reduce this or is it just part of the design?

 

[kripacharya]

Please state which chip you are talking about, and also quantify the phase noise measured ?

 

[vfone]

Yes, if you use higher clock frequency it will decrease the overall phase noise.
The phase noise of a 38 MHz crystal oscillator is slightly higher than the phase noise of a 32 kHz crystal oscillator, but the overall phase noise of the crystal oscillator is reduced by the number (N) of the PLL reference dividers on a rate of 20*LOG(N).

 

[kripacharya]

As a thumb rule, would it be correct to say that the higher the feedback divider ratio N (for a lower frequency ref clock), the higher the phase noise ? Add to this that presumably the PLL must be capable of generating multiple outputs with that same fixed crystal, so presumably a fractional-N divider is used, which adds to the noise spurs output ?