I'm studying VHDL at the moment using the latest reference books, and I would like you guys to give any recommendation on any good VHDL simulators and compliers too practice the codings.
GHDL: http://ghdl.free.fr
Looks ultra-good, but it is not very happy with the pseudo-IEEE packages (synopsys,mentor). Prefers using numeric_std, numeric_bit libs.
There is no really complete solution for logic synthesis that is open-source. But have a look at:
DGC: http://dgc.sourceforge.net
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