Recommendation flow of ASIC synthesis and P&R, please

[gaom9]

deffile in asic design

Hi,
Can anyone recommend a good flow of ASIC synthesis and P&R, please?
We will start a project of CPU synthesis and P&R. It is a much large project, and we do not know much about which tools flow is better. In P&R section, we are going to use the SOC encounter, but the synthesis section, we can not decide, DC, PC or PKS, and the main question is the floorplan when synthesis, how to do that? Beside these, what tools should we take care about?

Thank you!
Best regards!

 

[sunilbudumuru]

asic synthesis optimization

Hello friend,

Just check in "www.asic-dft.com" homepage. you will find the flow. You can click on "Physical Design Flow" Tab in the flow to know the flow of physical design.

To my knowledge, for synthesis DC is the best tool.

Regards,
Sunil Budumuru

 

[gaom9]

asic synthesis

Hi, sunilbudumuru
Thank you for your reply.
The web page is very helpful, but I still have a question about the floorplan. If I use the DC to synthesis, should I need anyother tools to do the floorplan for example: JupiterXT, how will they work together? What is the detailed flow of it？

Thank you!
Best regards.

 

[sunilbudumuru]

p&r deepchip

Hello friend,

See,
1. you synthesize ur design (RTL) (let us say)in one of the synthesis tool like "Design compiler". You will get the netlist.

2. Once the FE flow is done, u need to give the physical description of your design right. i mean if ur netlist is having any macros and all...
u should plan those macros and cells in proper locations.
Simply to make u understand, if u have to place TV, sofa, chairs in an empty hall, first you will plan how n where to place those things in that hall so that the hall looks good and have ample area for walk and also ease to access to all required material to one another.

Similarly, in the netlist you have PADs, MACROS CELLS etc. So first you have to plan the location of PADs MACROS etc that utilizes the optimal area of your chip AREA.
Here u r cing the physical representation of your chip.
Once you are done with the FLOOR PLAN to place those things in the respective places which is nothing but placement.
(I've kept the things much simple language to make u understand).

Any way, first thing u should make sure is in every stage, what are the INPUT FILES and what are the OUTPUT FILES. Think this way and start working u will came to know one by one.

Good Luck.

Sunil Budumuru

 

[gaom9]

def floorplan asic

Hi, Sunil Budumuru
Thank you for your wonderful reply. I have understood the importance of floor plan.
But I want to know which tool can do this? Can SOC encounter finish it? I know JupiterXT from Synopsys can do that, but I don't know how to make it work together with SOC encounter(we decided to use SOC encounter in P&R).
Will you give me more information, please?

Thank you!
Best regards!

 

[sunilbudumuru]

asic apr flow

ya happily you can do Floorplan, Placement and Routing using SOC Encounter. SOC Encounter is best suites to ur requirement.

However, you can see the input files required to start P&R in the following page.

**broken link removed**

cheers

Sunil Budumuru

 

[gaom9]

extract_physical_constraints

Hi, sunilbudumuru
I have got the step of floorplan using SOC encounter. And here is a video of "Automatic Floorplan Synthesis in the Cadence Encounter Digital Implementation System"
**broken link removed**

But I still have a question about the floorplan. As some one told me that JupiterXT of synopsys can feedback some placement imformation to DC to make a better synthesis, can SOC encounter do that? How to do that? Or is it needed to do so when the digital system is very large?


Thank you!
Best regards!

 

[sunilbudumuru]

what is .spef file in cadence encounter

Hay thank you for very informative video... and ..

DC n JupiterXT both are Synopsys tools so, there can be a better inter portability between the two. no doubt in it. and may achieve better optimization.

But at the same time you can do "in place optimization" using DC on the netlist that come out from SOCE. In general, if your design is large and timing critical u have to do those exercises. If you achieve your timing and area goals in the first iteration itself in SOCE, there is no need to fed the netlist from SOCE to DC again.

However, u can do your P&R with SOCE and Synthesis with DC and timing analysi with PT. mostly you dont find any compatibility issues with the files during the flow with these tools.

We have taped out the timing critical projects with the above mentioned flow without any issues.

-Sunil Budumuru.

 

[gaom9]

asic synthesis & apr flow

But at the same time you can do "in place optimization" using DC on the netlist that come out from SOCE. In general, if your design is large and timing critical u have to do those exercises. If you achieve your timing and area goals in the first iteration itself in SOCE, there is no need to fed the netlist from SOCE to DC again.


-Sunil Budumuru.

Hi, sunilbudumuru. Thank you for such an informative and important reply. That is what I need. But I can not find enough information about "In-place optimization" (IPO), would you please upload some here, please?
I read the DC user guide, and find the DC can use the Physical Constraints Extracted by the extract_physical_constraints Command from the Design Exchange Format (DEF) file which contains the information of the floorplan (extract_physical_constraints in.def -output output.tcl), so can we do the IPO as follow:

DC (first synthesis)---PT---First encounter to do the floorplan and then save the the floorplan result as the DEF file---feedback the DEF file to DC to do a second synthesis---PT---SOC encounter to do the final P&R

Is that right?

Thank you!
Best regards!

 

[sunilbudumuru]

synthesis & apr flow

Hi friend,
sorry for late reply.

thats correct u have to read "*.spef" file that is generated in SOCE and run "compile -in_place" to for in place optimization in DC.

And, u said, DEF file will be used for in-place optimization in DC. I am not sure we have to read DEF file also in CD for inplace optim. I haven't used DFF file for in place optimization process for my design. instead i've used SPEF file.

I knew, DEF file stores the scan chain information and used for ATPG process....


///// just ignore if u r not talking abour chain reordering ///////
I guess u r talking about "scan chain reordering" where we do use the DEF file. In this case,
SOCE will take the DEF file generated from DFTC and it will re-order the scan chains as per the input constraints to optimize the time and area..

www.asic-dft.com

 

[gaom9]

soc encounter read def

Hi, sunilbudumuru.

It doesn't matter, just a long happy holiday. Thank you for your reply.

Reference to your reply and www.asic-dft.com, I have make much clearer to my flow.

Scan chain reordering is also what I care about, and how to import the result of DFT compiler to SOCE is what I want to know, we talked about it today, but there is no answer.

In other words, before I do the Reorder Scan, I just need to load the DEF file output from DFTC?

There are too many tools in this flows to learn...

Best regards!

 

[sunilbudumuru]

asic synthesis flow

you have to give this DEF file to SOCE n it will reorder the scan chain as per your instructions...
n one thing is it is always good to be master in one of the tools (i mean in one area) in the flow, and knowledge on the other tools and knowing their behaviour is also equally important.

-Sunil Budumuru

 

[gaom9]

I got it, thank you very much.
I think this topic will help many people here.

Best regards!

 

[aravind]

Yesterday Deepchip has good article recent ASIC flow tool .
https://www.deepchip.com/items/0481-01.html

Regards
Aravind