Reason why my Scan-simulation is failing with post-layout netlist?

[dianin]

Hello Friends,

My scan-simulation is failing with post-layout netlist with SDF annotation. I'm seeing some timing violations in log file. Could anybody suggest how to debug it.

Also the post-layout STA was clean (e.g. no setup/hold violations in scan-mode), then why during simulation I'm seeing the violations, what could be the reason for that please let me know.

 

[kornukhin]

Does this violations happen on the flip-flops connected to input/inout ports? If yes, it could be because difference between IO constraints and arrival time in simulation.
Also, is violations occurs on scan path or logic path (SD or D input of FF)?
What kind of violations you get during simulation? Post log here, it can help.
How do you specify scan mode in STA tool? Using set_case_analysis on test_mode or on scan_enable?

Please, provide more information about the issue.